1. Field of the Invention
The present invention relates to data error, and in particular, to an error data correction circuit.
2. Background of the Related Art
The basic algorithm of a Hamming code uses a number (K+1) of parity bits when the number of data bits is 2.sup.k. For example, when the data is formed of 4-bits, (e.g., 2.sup.2 -bits), the parity bits become 3-bits in number.
In addition, the parity bit coding method determines that a data bit is 1 in each of the 3-bit parity bits by generating a group and adding the parity bit to a (2.sup.n)th position so that the number of 1s becomes 2n in the generated group. In other words, a table is formed by using 1st through 7th data bits based on the 4-bits of data and the 3-bit parity. In this case, the parity bits are bits 1, 2 and 4 (e.g., 2.sup.0, 2.sup.1 and 2.sup.2). Thereafter, 1st, 3rd, 5th, and 7th bits are grouped to determine the data bit is 1 in the first parity bit. The 2nd, 3rd, 6th, and 7th bits are grouped to determine whether the data bit is 1 in the second parity bit, and 4th, 5th, 6th, and 7th bits are grouped to determine whether the data bit is 1 in the third parity bit.
For example, if a data is 1011, the parity bit becomes 1st, 2nd, and 4th bits, so that one frame is formed of x, x, 1, x, 0, 1, and 1. Therefore, the parity bits are determined (e.g. by adding 1 or 0) so that the number of 1s becomes 2n in each parity group. In this manner, the 1st, 3rd, 5th, and 7th bits becomes 0, 1, 0, 1; the 2nd, 3rd, 6th, and 7th bits become 1, 1, 1, 1; and the 4th, 5th, 6th, and 7th bits become 0, 0, 1,1. Thus, the Hamming code final frame outputted from a sense amplifier is formed of seven bits being 0, 1, 1, 0, 0, 1, and 1.
In addition, an error detection method computes bit values of each parity group using an exclusive OR-gate. When the computed value is 0, it is judged that there is no error in the output from the sense amplifier. However, when the computed value is 1, it is judged that there is an error in the output from the sense amplifier.
In the case of 32 data bits (e.g., 2.sup.5 data bits), 6-bits are needed as parity bits. If a basic Hamming code is formed of 6-bits, the number of frames of a 6-bit parity is made different, so that it is difficult to form the logic of an exclusive OR-gate. Therefore, a modified Hamming code by that separates the bits 1 through 32 based on the different combinations on the assumption that there are two 1s or three 1s was disclosed. In the method, the error detection is performed in the same manner as the previous Hamming code method.
As shown in FIG. 1, the related art data correction circuit includes an error detection unit 10 for exclusively ORing outputs SA0 through SAn from a sense amplifier and for outputting error detection signals P0 through Pn. An error judgement unit 11 outputs an error judgement signal N1 based on the error detection signals P0 through Pn detected by the error detection unit 10. An error data correction unit 12 corrects the outputs SA0 through SAn from the sense amplifier in which an error occurred in accordance with the judgement signal N1 from the error judgement unit 11. An output buffer 13 outputs a data N4, which can be modified by the error data correction unit 12.
The error detection unit 10 is formed of exclusive OR-gates. The error judgement unit 11 includes a NOR-gate 11-1 for NORing only the data of 0 (zero) among the outputs from the error detection unit 10, and a NAND-gate 11-2, for NANDing only the data of 1 (one) among the outputs from the error detection unit 10.
The error data correction unit 12 includes a CMOS inverter 12-1 for inverting the output signals SA0 through SAn from the sense amplifier, a transmission gate 12-2 for transferring the output from the inverter 12-1 and a transmission gate 12-3. The transmission gate 12-3 transfers the output signals SA0 through SAn from the sense amplifier in accordance with the output from the NAND-gate 11-2, which was inverted by a CMOS inverter IN2. In addition, CMOS inverters IN3 and IN4 are coupled in series before an input to the output buffer 13.
The operation of the related art error data correction circuit will now be described. If the outputs SA0 through SAn from the sense amplifier (not shown) are normal, the outputs P0 through Pn from the error detection unit 10 are 0 (zero). Accordingly, the error judgement unit 11 outputs a high level error judgement signal N1.
Therefore, the transmission gate 12-3 of the error data correction unit 12 is turned on in accordance with a low level error judgement signal N1, which was inverted by the CMOS inverter IN2. Thus, the outputs SA0 through SAn from the sense amplifier are outputted through the transmission gate 12-3 and the CMOS inverters IN3 and IN4, respectively. The output buffer 13 receives the output from the error data correction unit 12, and outputs in accordance with an output enable signal DOen.
However, the output signal from the sense amplifier (not shown) may be delayed because of a process variation, etc., or an error data may be outputted. The delay of the output from the sense amplifier will now be described.
As shown in FIG. 2A, when the output SA0 from the sense amplifier (not shown) is delayed, the output from the error detection unit 10 becomes 1, and the outputs P1 through Pn become 0. In the drawings, broken lines denote a normal data output. In this case, the NOR-gate 11-1 of the error judgement unit 11 NORs the outputs P1 through Pn from the error detection unit 10, to output 1. Then, the NAND-gate 11-2 NANDs the output P0 from the error detection unit 10 and the output from the NOR-gate 11-1 to output a low level error judgement signal N1 at the time T1 as shown in FIG. 2B.
Since the transmission gate 12-2 of the error data correction unit 12 is turned on in accordance with a high level error judgement signal N1, which signal was inverted by the CMOS inverter IN2, the output SA0 from the sense amplifier is inverted by the CMOS inverter 12-1 and is outputted through the transmission gate 12-2. FIG. 2D illustrates the corrected output signal N4 from the transmission gate 12-2.
In addition, the output buffer 13 receives the corrected output N4 from the transmission gate 12-2 through the CMOS inverter IN3 and IN4. Accordingly, the output buffer 13 outputs the signal, as shown in FIG. 2F, in accordance with the output enable signal DOen as shown in FIG. 2E.
When the normal output SA0 from the sense amplifier is inputted at the time T2, the error judgement signal N1 becomes a high level. Then, the output SA0 from the sense amplifier is normally outputted through the transmission gate 12-3 and the inverters IN3 and IN4 to the output buffer 13.
As described above, in the related art error data correction circuit, when the outputs SA0 through SAn from the sense amplifier are delayed, an output from a corresponding amplifier in which the delay occurred is inverted and outputted. Then, when the signal from the sense amplifier is normally outputted, the non-inverted output from the sense amplifier is outputted. In addition, when the error data is outputted from the sense amplifier, the process is performed the same as the previous (delayed data) process.
Thus, the related art error data correction circuit has various disadvantages. When the output from the sense amplifier is delayed, the output of a transmission gate of the error data connection circuit is erroneously transited from a high level to a low level when the normal data actually arrives (e.g., between times T1 and T2 as shown in FIG. 2D). Then the output from the related art error correction circuit transmission gate transitions from the low level to a high level. Thus, the output buffer outputs a signal delayed by noise (glitch) as shown in FIG. 2F.